An important step in semiconductor device fabrication is electrical probe testing after some point in device fabrication has been reached. Typically, an electrical probe tester makes electrical contact with a particular die on a wafer at multiple test points. The electrical performance of the device structures may then be tested and probe data may be generated. Generally, probe data is utilized to calculate yields, fail rates, defect density, etc. Such data may be used to help improve device yield. Prior art methods include performing wafer probe testing and utilizing that data in traditional yield analysis techniques such as BITMAP, FIB, and yield modeling.
In addition to probe testing, semiconductor wafers may undergo inspection at various stages of device fabrication. Such inspection may be performed with optical or electron beam tools. Prior art methods inspection methods typically utilize die-based care area generation. In such methods, wafer inspection is performed on wafers in a repeating manner, such that a given care area for inspection is defined and then repeated uniformly by die across the given wafer. Prior art methods of wafer inspection include defining fixed care areas which repeat by die across the wafer with no prior knowledge of known bad areas. Each die is then inspected for defects at the repeating care areas.
Unfortunately, defects may not necessarily repeat from die to die. Therefore, prior art methods are often inefficient due to inspecting more area than required. In addition, prior art yield improvement techniques often operate without all possible data (such as defect images which would result from wafer inspection).
It is within this context that embodiments of the present invention arise.